1. Field of the Invention
The present invention relates to the field of programmable logic devices. Specifically, the invention is designed to perform a cascadable bus based crossbar switching function.
2. Related Art
Programmable logic devices are often applied to perform switching functions. This utilization is especially prevalent in the field of data communications. Programmable logic device (PLD) structure, by design, is conducive to orderly data flowthrough, commonly via interconnected matrices of vertical and horizontal conductors. Interconnections are enabled in one modality by crossbar switching structures embedded within the PLD.
In performing switching functions, PLDs receive incoming data streams, route these streams according to a designed-in or field configured routing fabric, perform logic upon the data per a sequence of programmed instructions, switch the data streams to place them in a designated output configuration, and send off outgoing data streams to specified destinations accordingly.
Data streams predominantly flow through PLD structures in bus based modalities, rather than as individual bits. Most PLD based switching applications utilize simultaneous switching of buses of typically four, eight, ten, or sixteen wires, rather than individual wires. However, conventionally, data streams are switched by PLDs bit by bit, individually. Implementing a bit by bit switch is inefficient and costly. Conventional PLD switching implementations may contain small logic elements, each of which can be used to implement a single function of up to 4 inputs. FIG. 1 shows how a single switch 100CA with one-bit 16-input 12CA, one-output 13CA can be implemented using logic elements 4CA in accordance with-the conventional approach. To implement a ten-bit 16-input 16-output switch, 160 copies of the circuit 100CA in Conventional Art FIG. 1 are required (because there are 16 outputs, each with 10 bits).
The inefficiency of switching data streams by the conventional art adds expense to the switching function which manifests as lower than optimal switching speeds and demands on logic density. This results in architecture requiring a costly high logic density dedicated to switching, cascading layers of logic circuits for implementation of switching, and also results in outputs delayed by the cumulative, successive operation delays of each logic stage. Such high logic density mandated for dedication to switching functions ties up valuable circuit space and utilizes power then unavailable for other logic applications. Making conventional PLD switching circuits configurable exacerbates this problem. This further reduces efficiency and increases cost. These limitations impact applications requiring combinations of high speed, low switching dedicated logic density, low power consumption, and modest cost, and may preclude certain applications.
In the conventional art, as shown by U.S. Pat. No. 6,060,903, data streams flow through PLDs bi-directionally. Conventional Art FIG. 2 illustrates the approach taken in this conventional art. Both the vertical buses 101CA-V and horizontal buses 101CA-H therein may interchangeably carry input and output; thus input ports and output ports are interchangeable, and data streams may flow in any direction through the device. In this architecture, the ports of the bi-directional switches can be configured as either input ports or as output ports. However, bi-directional switches with combination input/output ports are relatively slow. While this offers some measure of flexibility, it is inefficient. Certain PLD switching applications may not require the bi-directionality offered in the conventional art, and thus may be encumbered by the restrictions in speed and other performance. These encumbrances limit certain PLD switching applications, and may repress some.
Certain switching applications utilizing PLDs require extremely large scale switching functions. In such applications, the number of inputs, the number of outputs, or both may exceed the capacity devoted to switching in a single PLD structure. In the conventional art, this constrains the application of single PLDs, demanding multistaging, which requires additional PLDs. In some applications, this constraint may be a barrier to large scale PLD switching.
Further, switching applications may require the fixing of the location of specific data signals in a specific order for output. Yet, switching within PLD structures generally disarrays order between inputs and outputs. Without the imposition of this order at the proper outputs, applications depending on orderly PLD switching and output are effectively precluded. Routing of signals through a PLD as the signals undergo switching therein conventionally poses a crucial problem to achieve this specified order at the designated locations.
Accordingly, what is needed is a configurable circuit, which allows bus based switching of data streams within programmable logic devices wherein data is switched at a bus level, each bus in its entirety, and which is optimized for switching many large buses. What is also needed is a circuit which performs switching within programmable logic devices wherein higher performance is achieved by limiting data flow, from input to output, to a single direction. Further, what is needed is a method and circuit thereof for cascading programmable logic device switching circuits with other such circuits, which enables switching on a scale much larger than would be possible with conventional switching. Further still, what is needed is a switching circuit for programmable logic devices which is configurable for designating a specific, fixed output signal order relative to the input signals.
The present invention provides a configurable circuit which allows bus based switching of data streams within programmable logic devices wherein data is switched at a bus level, each bus in its entirety, and which is optimized for switching many larger buses. The present invention also provides a circuit which performs switching within programmable logic devices wherein higher performance is achieved by limiting data flow, from input to output, to a single direction. Further, the present invention provides a method and circuit thereof for cascading programmable logic device switching circuits with other such circuits, which enables switching on a scale much larger than would be possible with conventional switching. Further still, the present invention provides a switching circuit for programmable logic devices which is configurable for designating a specific, fixed output signal order relative to the input signals.
One embodiment of the present invention provides a configurable crossbar circuit enabling bus based switching of data streams within programmable logic devices wherein data is switched at a bus level. This crossbar switching structure, in accordance with this embodiment, is optimized for switching many larger buses. In this embodiment, the crossbar circuit is embedded, as an integral part, within the programmable logic device. In the present embodiment, each data bus is switched in its entirety, as a bus unit. Bus based switching in accordance with the present embodiment of the present invention efficiently accords with the predominant flow of data through PLD is structures in bus based modalities. Bus based switching in accordance with the present embodiment implements higher performance switching, e.g., efficient switching at higher speeds, and with lower cost in terms of the logic density demanded by the switching function, itself. The configurability of the circuit in the present embodiment accords a useful measure of flexibility in the design of programmable logic device applications.
In another embodiment of the present invention, a configurable crossbar switching circuit performs switching within programmable logic devices wherein data flow, from an input to an output, is limited to a single direction. In this embodiment, at any given time, data may flow unidirectionally; e.g., data ports may not simultaneously function as inputs and outputs. Such unidirectional circuit operation yields higher performance in terms of switching speed and efficiency. Further, unidirectional switching may be performed without a complex circuit design, in as much as structure supporting bi-directional operation is obviated. The density of logic demanded by the switching application itself, is reduced accordingly in the present embodiment. This has the additional advantage of freeing up logic, circuit space, and power availability for other programmable logic device applications.
In a further embodiment, the present invention provides a method and circuit thereof for cascading programmable logic device switching circuits with other such circuits. In one implementation, a switching function is enabled is between a number of inputs, e.g., fewer than the number of inputs to which a single crossbar switch may be limited, and a number of outputs in excess of the number of outputs to which a single crossbar switch is limited. In another implementation, a switching function is enabled wherein switching is. accomplished between a number of inputs in excess of the number of inputs to which a single crossbar switch is limited and a number of outputs, e.g., fewer than the number of outputs to which a single crossbar switch may be limited. In yet another implementation, a switching function may be accommodated between a number of inputs and a number of outputs, both numbers in excess of the number of each to which a single crossbar switch may be limited.
The cascadability of programmable logic device crossbar switches enables switching on a scale much larger than would be possible with conventional switching. In accordance with this embodiment of the present invention, any number of inputs may be switched with any number of outputs by freely cascading crossbar switching circuits, one upon the other, in the design, fabrication, and configuration of crossbar switches embedded in programmable logic devices. Effectively, this cascading of individual, relatively small crossbar switches within a programmable logic device implements a larger switch.
In yet a further embodiment, the present invention provides a crossbar switching circuit for programmable logic devices which is configurable for designating a specific, fixed output signal order relative to the input signals. This has the advantage of permitting flexibility in circuit design and fabrication, and effectively broadens the application spectrum for programmable logic devices embedding crossbar switches incorporating the present embodiment.